Analysis and comparison of the three most popular

  • Detail

Analysis and comparison of three common SOC on-chip buses

Abstract: with the development of integrated circuit design technology, in system on chip (SOC), more and more functional IP core components are used to form the system. Bus is the main way to connect these components. At present, several companies and organizations have developed a variety of bus systems for SoC design. This paper introduces three kinds of on-chip buses commonly used in SOC, AMBA and W, sorts out and cleans the experimental machine accordingly, analyzes and compares their characteristics, and expounds their application scope according to their different characteristics

key words: SOC on-chip bus AMBA wishbone Avalon


embedded system is a hot spot in the development of computer industry today. With the rapid development of VLSI, the semiconductor industry has entered the era of deep submicron. The feature size of devices is getting smaller and smaller, and the scale of chips is getting larger and larger. Millions to hundreds of millions of transistors can be integrated on a single chip. Such intensive integration enables us to integrate the functions previously realized by several chips such as CPU and several i/o interfaces on a small chip, and a powerful and complete system is composed of a single integrated circuit, which is commonly referred to as system on chip (SOC). Due to its complete functions, SOC has gradually become the mainstream of embedded system development

Compared with on-board system, SOC has many advantages:

① make full use of IP technology, reduce product design complexity and development cost, and shorten product development time

② single chip integrated circuit can effectively reduce system power consumption

③ reduce the number of external pins of the chip and simplify the complexity of system processing

④ reduce the signal transmission between the peripheral drive interface unit and the circuit board, and accelerate the speed of data transmission and processing

⑤ the embedded circuit can reduce or even avoid the system signal crosstalk caused by the signal transmission of the circuit board

In the design process of SOC, the most distinctive is IP multiplexing technology. That is, select the IP (give IP definition) core of the required function and integrate it into a chip. Because the design of IP core varies greatly, the connection of IP core becomes the key to construct SOC. On chip bus (OCB) is the most common technical means to realize the connection of IP cores in SOC. It realizes the data communication between IP cores by bus. Unlike the on-board bus, the on-chip bus does not drive the signals and connectors on the backplane, so it is simpler and faster to use. An on-chip bus specification generally needs to define the relationships of drivers, timing, strategies and so on in the process of initialization, arbitration, request transmission, response, sending and receiving among various modules

due to the different application scope of on-chip bus and on-board bus, there are great differences. Its main characteristics are as follows:

① on-chip bus should be as simple as possible. First, the structure should be simple, which can occupy less logical units; Secondly, the timing should be simple to improve the speed of the bus; The third interface should be simple, which can reduce the complexity of connecting with the IP core

② the on-chip bus has greater flexibility. Because the system on chip is widely used, and different applications have different requirements for the bus, the bus on chip has greater flexibility. First, the data and address width of most on-chip buses are variable. For example, AMBA AHB supports 32-bit to 128 bit data bus width; Secondly, the interconnection structure of some on-chip buses is variable. For example, wishbone Bus supports four interconnection modes: point-to-point, data flow, shared bus and cross switch; Third, the arbitration mechanism of some on-chip buses is flexible and variable. For example, the arbitration mechanism of wishbone bus can be completely customized by users

③ the power consumption of on-chip bus should be reduced as much as possible. Therefore, in practical application, various signals on the bus should be kept unchanged as much as possible, and unidirectional signal lines are used to reduce power consumption and simplify timing at the same time. The above three on-chip bus input data lines and output data lines are separated, and there is no signal multiplexing phenomenon

there are two implementation schemes of on-chip bus. One is to choose the internationally open and common bus structure; The second is to independently develop on-chip bus according to specific fields. This paper discusses three kinds of on-chip bus standards used in SoC at present - AMBA of arm, wishbone of silicon and Avalon of Altera, and analyzes and compares their characteristics

1 AMBA bus

amba (advanced microcontroller bus architecture) bus specification is a bus standard designed by arm company for high-performance embedded systems. It is independent of processor and manufacturing technology, and enhances the reusability of peripherals and system macro units in various applications. AMBA bus specification is an open standard, which can be obtained from arm for free. At present, AMBA has many third-party support and is adopted by more than 90% of the partners of arm company. In the SOC Design Based on ARM processor core, it has become one of the widely supported existing interconnection standards. AMBA bus specification 2.0 was released in 1999. The advanced high performance bus (AHB) introduced by this specification is the main form of AMBA implementation at this stage. The key of AHB is to define the interface and interconnection, in order to achieve the maximum bandwidth of the interface and interconnection under any process conditions. The AHB interface has been separated from the interconnection function. It is no longer just a bus, but an interconnection system with interface modules

The main design purposes of AMBA bus specification are as follows: ① meet the rapid development requirements of embedded system products with one or more CPUs or DSPs; ② Increase the independence of design technology to ensure that a variety of reusable IP cores can be successfully transplanted to different systems, suitable for full customization, standard cells, gate arrays and other technologies; ③ Promote the modular design of the system to increase the independence of the processor; ④ Reduce the demand for the underlying silicon to make the off chip operation and test communication more effective

amba bus is a multi bus system. The specification defines three different types of buses that can be used in combination: AHB (advanced high performance bus), a3d printing is deeply changing the world sb (advanced system bus) and APB (advanced peripheral bus)

the typical AMBA based SoC core is shown in Figure 1. Among them, high-performance system bus (AHB or ASB) is mainly used to meet the bandwidth requirements between CPU and memory. High speed devices such as CPU, on-chip memory and DMA devices are connected to it, while most of the low-speed external devices of the system are connected to the low bandwidth bus APB. A bridge (AHB/ASB APB bridge) is used to connect the system bus and peripheral bus

The AHB of

amba is suitable for system modules with high performance and high clock frequency. As the backbone bus of high-performance system, it is mainly used to connect high-performance and high-throughput devices, such as CPU, on-chip memory, DMA devices and DSP or other coprocessors. Its main features are as follows:

◇ support multiple bus master controllers

◇ support burst, split, pipelining and other data transmission methods

◇ single cycle bus master dandelion natural rubber equipment control power conversion

◇ 32-128 bit data bus width

◇ it has access protection mechanism to distinguish privileged mode and non privileged mode access, instruction and data reading, etc

◇ the maximum data burst transmission is 16 segments

◇ address space 32 bits

◇ support byte, halfword and word transmission

amba ASB is suitable for high-performance system modules. When it is unnecessary to apply the high-speed characteristics of AHB, ASB can be selected as the system bus. It also supports the connection between processors, on-chip memory and off chip processor interfaces and low-power external macro units. Its main characteristics are similar to AHB, the main difference is that it uses the same bidirectional data bus to read and write data

The APB of

amba is suitable for low-power external devices. It has been optimized to reduce power consumption and the complexity of external interfaces; It can be connected to two system buses. Its main features are as follows:

◇ low speed, low power external bus

◇ single bus master controller

◇ very simple. With clock and reset, there are only 4 control signals in total

◇ 32-bit address space

◇ maximum 32-bit data bus

◇ the read data bus is separated from the write data bus

2 wishbone bus

wishbone was first proposed by silicon and has now been handed over to opencores for maintenance. Due to its openness, many user groups, especially some free IP cores, have adopted the wishbone standard

The wishbone bus specification is a system on chip IP core interconnection architecture. It defines a common logical interface between IP cores, reduces the difficulty of system component integration, improves the reusability, reliability and portability of system components, and accelerates the speed of selecting hydrogen regulated PP resin with low odor for product marketization. Wishbone bus specification can be used for soft core, solid core and hard core. It has no special requirements for development tools and target hardware, and is compatible with almost all existing comprehensive tools, which can be implemented with a variety of hardware description languages

The purpose of wishbone bus specification is to serve as a general interface between IP cores, so it defines a set of standard signals and bus cycles to connect different modules, rather than trying to standardize the functions and interfaces of IP cores

wishbone bus structure is very simple, it only defines a high-speed bus. In a complex system, the multi-level bus structure of two wishbone buses can be adopted: one is for the high-performance system part, the other is for the low-speed peripheral part, and an interface is required between the two. Although this interface takes up some circuit resources, it is much simpler than designing and connecting two different buses. Users can customize the wishbone standard as needed, such as byte alignment and the meaning of flag bits (tags), and add some other features. An interconnection structure of wishbone is shown in Figure 2

flexibility is another advantage of wishbone bus. Due to the diversity of IP cores, there is no unified indirect way. In order to meet the needs of different systems, wishbone bus provides four different ways of IP core interconnection:

◇ point-to-point, which is used for the direct interconnection of two IP cores

◇ data flow, which is used for data concurrent transmission between multiple serial IP cores

◇ shared bus, multiple IP cores share a bus

◇ crossbar switch (Figure 2), which connects multiple master-slave components at the same time, improves the system throughput

there is also an off chip connection mode, which can be connected to any of the above mutual contacts. For example, two different chips with a wishbone interface can be connected point-to-point

the main features of wishbone bus are as follows:

◆ all applications are applicable to the same bus architecture

◆ it is a simple and compact logical IP core hardware interface, which can be realized with few logical units

◆ the timing is very simple

◆ bus of master/slave structure, supporting multiple bus master devices

◆ 8~64 bit data bus (expandable)

◆ single cycle reading and writing

◆ support all commonly used bus data transmission protocols, such as single byte read-write cycle, block transmission cycle, control operation and other bus transactions

◆ branch

Copyright © 2011 JIN SHI